Increasing electromigration resistance in an interconnect structure of a semiconductor device by forming an alloy

ABSTRACT

By introducing a metallic species into an exposed surface area of a copper region, the electromigration behavior of this surface area may be significantly enhanced. The incorporation of the metallic species may be accomplished in a highly selective manner so as to not unduly affect dielectric material positioned adjacent to the metal region, thereby essentially avoiding undue increase of leakage currents.

BACKGROUND OF THE INVENTION

1. FIELD OF THE INVENTION

Generally, the present disclosure relates to the formation ofmicrostructures, such as advanced integrated circuits, and, moreparticularly, to the formation of conductive structures, such ascopper-based metallization layers, and techniques to reduceelectromigration and other stress-induced mass transport effects duringoperation.

2. DESCRIPTION OF THE RELATED ART

In the field of fabricating modern microstructures, such as integratedcircuits, there is a continuous drive to steadily reduce the featuresizes of microstructure elements, thereby enhancing the functionality ofthese structures. For instance, in modern integrated circuits, minimumfeature sizes, such as the channel length of field effect transistors,have reached the deep sub-micron range, thereby increasing performanceof these circuits in terms of speed and/or power consumption. As thesize of individual circuit elements is reduced with every new circuitgeneration, thereby improving, for example, the switching speed of thetransistor elements, the available floor space for interconnect lineselectrically connecting the individual circuit elements is alsodecreased. Consequently, the dimensions of these interconnect lines arealso reduced to compensate for a reduced amount of available floor spaceand for an increased number of circuit elements provided per unit diearea, as typically the number of interconnections required increasesover-proportionally relative to the number of circuit elements. Thus, aplurality of stacked “wiring” layers, also referred to as metallizationlayers, is usually provided, wherein individual metal lines of onemetallization layer are connected to individual metal lines of anoverlying or underlying metallization layer by so-called vias. Despitethe provision of a plurality of metallization layers, reduced dimensionsof the interconnect lines are necessary to comply with the enormouscomplexity of, for instance, modern CPUs, memory chips, ASICs(application specific ICs) and the like. The reduced cross-sectionalarea of the interconnect structures, possibly in combination with anincrease of the static power consumption of extremely scaled transistorelements, may result in considerable current densities in the metallines, which may even increase with every new device generation.

Advanced integrated circuits, including transistor elements having acritical dimension of 0. μm and even less, may, therefore, typically beoperated at significantly increased current densities of up to severalkA per cm² in the individual interconnect structures, despite theprovision of a relatively large number of metallization layers, owing tothe significant number of circuit elements per unit area. Operating theinterconnect structures at elevated current densities, however, mayentail a plurality of problems related to stress-induced linedegradation, which may finally lead to a premature failure of theintegrated circuit. One prominent phenomenon in this respect is thecurrent-induced mass transport in metal lines and vias, also referred toas “electromigration.” Electromigration is caused by momentum transferof electrons to the ion cores in the conductors, resulting in a netmomentum in the direction of electron flow. In particular, at highcurrent densities, a significant collective motion or directed diffusionof atoms may be caused due to electromigration in the interconnectmetal, wherein the presence of respective diffusion paths may have asubstantial influence on the displaced amount of mass resulting from themomentum transfer. Thus, electromigration may lead to the formation ofvoids within and hillocks next to the metal interconnect, therebyresulting in reduced performance and reliability or complete failure ofthe device. For instance, aluminum lines embedded into silicon dioxideand/or silicon nitride are frequently used as metal for metallizationlayers, wherein, as explained above, advanced integrated circuits havingcritical dimensions of 0.1 μm or less, may require significantly reducedcross-sectional areas of the metal lines and, thus, increased currentdensities, which may render aluminum less attractive for the formationof metallization layers.

Consequently, aluminum is being replaced by copper, a material withsignificantly lower resistivity and improved resistance toelectromigration even at considerably higher current densities comparedto aluminum. The introduction of copper into the fabrication ofmicrostructures and integrated circuits comes along with a plurality ofsevere problems residing in copper's characteristic to readily diffusein silicon dioxide and a plurality of low-k dielectric materials, whichare typically used in combination with copper in order to reduce theparasitic capacitance within complex metallization layers. In order toprovide the necessary adhesion and to avoid the undesired diffusion ofcopper atoms into sensitive device regions, it is, therefore, usuallynecessary to provide a barrier layer between the copper and thedielectric material in which the copper-based interconnect structuresare embedded. Although silicon nitride is a dielectric material thateffectively prevents the diffusion of copper atoms, selecting siliconnitride as an interlayer dielectric material may be less than desirable,since silicon nitride exhibits a moderately high permittivity, therebyincreasing the parasitic capacitance of neighboring copper lines, whichmay result in non-tolerable signal propagation delays. Hence, a thinconductive barrier layer that also imparts the required mechanicalstability to the copper is usually formed to separate the bulk copperfrom the surrounding dielectric material, thereby reducing copperdiffusion into the dielectric materials and also reducing the diffusionof unwanted species, such as oxygen, fluorine and the like, into thecopper. Furthermore, the conductive barrier layers may also providehighly stable interfaces with the copper, thereby reducing theprobability of significant mass transport at these interfaces, which aretypically a critical region in view of increased diffusion paths.Currently, tantalum, titanium, tungsten and their compounds, withnitrogen and silicon and the like are preferred candidates for aconductive barrier layer, wherein the barrier layer may comprise two ormore sub-layers of different composition to meet the requirements interms of diffusion suppressing and adhesion properties.

Another characteristic of copper significantly distinguishing it fromaluminum is the fact that copper may not be readily deposited in largeramounts by chemical and physical vapor deposition techniques, inaddition to the fact that copper may not be efficiently patterned byanisotropic dry etch processes, thereby requiring a process strategythat is commonly referred to as the damascene or inlaid technique. Inthe damascene process, first a dielectric layer is formed, which is thenpatterned to include trenches and/or vias which are subsequently filledwith copper, wherein, as previously noted, prior to filling in thecopper, a conductive barrier layer is formed on sidewalls of thetrenches and vias. The deposition of the bulk copper material into thetrenches and vias is usually accomplished by wet chemical depositionprocesses, such as electroplating and electroless plating, therebyrequiring the reliable filling of vias with an aspect ratio of 5 andmore with a diameter of 0.3 μm or even less, in combination withtrenches having a width ranging from 0.1 μm to several μm.Electrochemical deposition processes for copper are well established inthe field of electronic circuit board fabrication. However, thevoid-free filling of high aspect ratio vias is an extremely complex andchallenging task, wherein the characteristics of the finally obtainedcopper-based interconnect structure significantly depend on processparameters, materials and geometry of the structure of interest. Sincethe geometry of interconnect structures is substantially determined bythe design requirements and may, therefore, not be significantly alteredfor a given microstructure, it is of great importance to estimate andcontrol the impact of materials, such as conductive and non-conductivebarrier layers, of the copper microstructure and their mutualinteraction on the characteristics of the interconnect structure toinsure both high yield and the required product reliability. Inparticular, it is important to identify, monitor and reduce degradationand failure mechanisms in interconnect structures for variousconfigurations to maintain device reliability for every new devicegeneration or technology node.

Accordingly, a great deal of effort has been made in investigating thedegradation of copper interconnects, especially in combination withlow-k dielectric materials having a relative permittivity of 3.1 orless, in order to find new materials and process strategies for formingcopper-based lines and vias with a low overall permittivity. Althoughthe exact mechanism of electromigration in copper lines is still notquite fully understood, it turns out that voids positioned in and onsidewalls and especially at interfaces to neighboring materials may havea significant impact on the finally achieved performance and reliabilityof the interconnects.

One prominent failure mechanism which is believed to significantlycontribute to a premature device failure is the electromigration-inducedmaterial transport, particularly at an interface of the copper lines tothe dielectric cap layer, which may be deposited after filling in thecopper on the basis of the electrochemical deposition techniques. Theinterface characteristics may, therefore, be determined by the previousmanufacturing steps, resulting in a specific texture of the copper, andthe material characteristics of the cap material, which is frequentlyprovided in the form of silicon nitride, silicon carbide,nitrogen-containing silicon carbide and the like. Recent researchresults seem to indicate that the electromigration behavior of thecopper/cap layer interface may be improved by providing metallicimpurities at the interface. It is believed that these impurity atomsmay tightly adhere to the copper surface and therefore suppress themigration of copper atoms, which may otherwise be caused by the momentumtransfer of the electrons at the high current density that typicallyprevails in the metal line during operation. It has, therefore, beenproposed to form copper alloys on the exposed copper surface byselective electrochemical deposition techniques prior to depositing thedielectric material. Although enhanced electromigration behavior may beachieved, the contamination of the surrounding dielectric material bythe metallic components during the selective deposition technique mayresult in increased line-to-line leakage.

The present disclosure is directed to various methods and devices thatmay avoid, or at least reduce, the effects of one or more of theproblems identified above.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order toprovide a basic understanding of some aspects of the invention. Thissummary is not an exhaustive overview of the invention. It is notintended to identify key or critical elements of the invention or todelineate the scope of the invention. Its sole purpose is to presentsome concepts in a simplified form as a prelude to the more detaileddescription that is discussed later.

Generally, the subject matter disclosed herein relates to enhancedtechniques for improving the electromigration behavior in themetallization structure of advanced semiconductor devices. To this end,an appropriate metallic species may be provided at a surface of themetal while substantially avoiding the metallic species in the adjacentdielectric material in the completed metallization layer so as to reducethe risk of creating increased leakage currents. In illustrative aspectsdisclosed herein, appropriate thin films including the metallic speciesmay be selectively deposited on the basis of an appropriately prepareddeposition mask, thereby substantially avoiding a contamination of theadjacent dielectric material. In other illustrative aspects, anappropriate material layer including the metallic species may bedeposited and patterned, thereby removing the metallic species from thedielectric material, wherein a subsequent diffusion process may finallyresult in the incorporation of the metallic species in the underlyingmetal region. In other illustrative aspects, the metallic species may beefficiently incorporated into a surface area by particle bombardment,such as ion implantation, plasma treatment and the like.

One illustrative method disclosed herein comprises forming a mask abovea metal region formed in a dielectric material of a metallization layerof a semiconductor device, wherein the mask exposes a surface of themetal region and covers the dielectric material. The method furthercomprises applying a metallic species through the mask to the exposedsurface of the metal region and removing the mask. Additionally, themethod comprises forming a dielectric cap material above themetallization layer, wherein the dielectric cap material covers thesurface containing the metallic species.

A further illustrative method disclosed herein comprises forming a metallayer above a dielectric layer of a metallization layer of asemiconductor device so as to fill an opening in the dielectric layer.The method further comprises performing an implantation process tointroduce a metallic species through an exposed surface of the metallayer. Moreover, the method comprises removing excess material of themetal layer from the dielectric layer to form a metal region in thedielectric layer, wherein the metal region has a surface comprising themetallic species.

A still further illustrative method disclosed herein comprises forming avia opening in a dielectric layer, wherein the via opening extends toand exposes a portion of a first metal region formed in a firstmetallization layer of a semiconductor device. The method additionallycomprises performing an ion implantation process to introduce a metallicspecies into the exposed portion of the first metal region. Finally, thevia opening is filled with a metal.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIGS. 1 a-1 c schematically illustrate cross-sectional views of asemiconductor device during various manufacturing stages in forming ametallization layer including a metal region having a metallic speciesselectively formed in a surface area thereof, according to illustrativeembodiments;

FIGS. 1 d-1 h schematically illustrate the semiconductor device duringvarious manufacturing stages, wherein a metallic species may be formedon the surface of a metal line in an intermediate stage of forming themetal line, according to illustrative embodiments;

FIGS. 1 i-1 j schematically illustrate the semiconductor device duringvarious manufacturing stages in selectively providing a metal layercontaining an appropriate metallic species for enhancing theelectromigration behavior of an underlying metal line, according to yetother illustrative embodiments;

FIG. 1 k schematically illustrates a cross-sectional view of ametallization layer during a diffusion process for selectively driving ametallic species into the surface of a metal layer, according to stillfurther illustrative embodiments; and

FIGS. 1 l-1 m schematically illustrate cross-sectional views of thesemiconductor device when forming a via opening through which thespecies may be incorporated into an exposed surface portion of a metalregion, according to still other illustrative embodiments.

While the subject matter disclosed herein is susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and are herein described indetail. It should be understood, however, that the description herein ofspecific embodiments is not intended to limit the invention to theparticular forms disclosed, but on the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

Various illustrative embodiments are described below. In the interest ofclarity, not all features of an actual implementation are described inthis specification. It will of course be appreciated that in thedevelopment of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

The present subject matter will now be described with reference to theattached figures. Various structures, systems and devices areschematically depicted in the drawings for purposes of explanation onlyand so as to not obscure the present disclosure with details that arewell known to those skilled in the art. Nevertheless, the attacheddrawings are included to describe and explain illustrative examples ofthe present disclosure. The words and phrases used herein should beunderstood and interpreted to have a meaning consistent with theunderstanding of those words and phrases by those skilled in therelevant art. No special definition of a term or phrase, i.e., adefinition that is different from the ordinary and customary meaning asunderstood by those skilled in the art, is intended to be implied byconsistent usage of the term or phrase herein. To the extent that a termor phrase is intended to have a special meaning, i.e., a meaning otherthan that understood by skilled artisans, such a special definition willbe expressly set forth in the specification in a definitional mannerthat directly and unequivocally provides the special definition for theterm or phrase.

The subject matter of the present disclosure relates to manufacturingtechniques for semiconductor devices in which a metallic species may beintroduced into a metal region in a selective manner, that is, in amanner such that significant contamination of surface areas of thedielectric material may be avoided. For this purpose, the metallicspecies, which may be considered as an alloy-forming species, may bebrought into contact with the metal region under considerationsubstantially without contacting the adjacent dielectric material orwherein a thin surface portion of the dielectric material may be removedtogether with any possible contaminants, when metallic species may beintroduced in an intermediate manufacturing stage for forming themetallization layer under consideration. Consequently, the advantageouseffects of a metal species, which in some illustrative embodiments maybe provided in the form of an atomic species having an atomic radiusthat is greater than the radius of copper, may therefore be obtainedsubstantially without negatively affecting the characteristics of thedielectric material. In this manner, the inter-diffusion of the metallicspecies into deeper areas of the metal and into the dielectric capmaterial may be reduced. The selective positioning of metallic speciesat and within the surface of the metal region under consideration may beaccomplished by appropriately designed deposition and/or diffusionprocesses, depending on material characteristics, while, in otherillustrative aspects, implantation processes, for instance based onappropriately designed implantation masks or on the basis of a“self-masking” regime, may be performed at appropriate manufacturingstages in order to enhance the surface characteristics of metal regions,such as copper-containing regions, with respect to the electromigrationperformance.

FIG. 1 a schematically illustrates a cross-sectional view of asemiconductor device 100 in an advanced manufacturing stage. Thesemiconductor device 100 may comprise a substrate 101, which mayrepresent any appropriate carrier material, such as semiconductivematerials, insulating materials and the like, for forming therein andthereabove respective semiconductive features, such as transistors andthe like. For example, the substrate 101 may represent a substantiallycrystalline semiconductor material, such as silicon, germanium, asemiconductor compound and the like. In other cases, the substrate 101may comprise, at least partially, an insulating layer, above which anappropriate material layer may be provided which is suitable for formingtherein and thereon circuit elements. For convenience, any such circuitelements are not shown in FIG. 1 a. Thus, unless otherwise stated in thespecification and/or the appended claims, the subject matter disclosedherein should not be considered as being restricted to any specificsemiconductor material and carrier material for the substrate 101,including a device layer with circuit elements such as transistors andthe like.

The semiconductor device 100 as shown in FIG. 1 a may further comprise alayer 110, which may represent a metallization layer, such as the veryfirst metallization layer, which may connect to respective circuitelements on the basis of a contact structure (not shown) and the like.For convenience, the layer 110 may be referred to as a metallizationlayer which may comprise a dielectric material 111 that may comprise anyappropriate material or material composition, as required. For instance,the dielectric material 111 may comprise a low-k dielectric material,i.e., a material having a relative permittivity of 3.0 or less in orderto reduce the parasitic capacitance with respect to neighboring metalregions. Furthermore, the metallization layer 110 may comprise a metalregion 112, which may be substantially comprised of a highly conductivemetal, such as copper, silver, alloys thereof and the like, while, inother cases, contact materials, such as tungsten and the like, may beincorporated in the metal region 112. The metal region 112 may furthercomprise conductive barrier materials if metals exhibiting increaseddiffusion activity may be considered, such as copper. In some cases, themetallization layer 110 may further comprise a dielectric cap layer, forinstance in the form of silicon nitride, silicon carbide,nitrogen-containing silicon carbide and the like, when a direct contactof the metal region 112 with a further metallization layer 120, i.e., adielectric material 121 thereof, is considered inappropriate. The secondmetallization layer 120 may further comprise a metal region 122, forinstance in the form of a trench 122A and a via 122B. Furthermore, inthe embodiment shown, the metal region 122 may comprise a highlyconductive metal, such as copper, which may require a confinement by anappropriately designed barrier layer 123. For example, appropriatebarrier materials in a copper-based metallization regime are tantalum,tantalum nitride, titanium, titanium nitride, a plurality of compoundssuch as cobalt, tungsten, phosphorous, or a compound of cobalt,tungsten, boron, compounds of nickel, molybdenum, boron and the like. Aspreviously discussed, the electromigration effects at an interfacebetween the barrier layer 123 and the highly conductive metal in themetal region 122 may be less pronounced, while, typically, a dominantfailure mechanism may occur at a surface 122S of the region 122 whenbrought into contact with a dielectric material of a followingmetallization layer.

The semiconductor device 100 as shown in FIG. 1 a may be formed on thebasis of well-established process techniques. That is, circuit elements,possibly in combination with other microstructural features, may beformed at any appropriate level above the substrate 101, as previouslyexplained, wherein transistor elements may be formed on the basis ofcritical dimensions on the order of magnitude of 50 nm and less, as aretypically used in sophisticated integrated circuits, such as CPUs andthe like. Thereafter, an appropriate contact structure, for instance thelayer 110, may be formed to provide electrical connection to conductivesemiconductor areas of the circuit elements previously formed. Next, oneor more metallization levels may be provided, when the layer 110 may notrepresent the very first metallization layer. Thereafter, the dielectricmaterial 111 may be deposited on the basis of any appropriate technique,wherein it should be appreciated that well-established materialcompositions, for instance including etch stop layers and the like, maybe incorporated in the material 111. Subsequently, well-establishedpatterning regimes may be used to form openings corresponding to themetal region 112, which may typically be provided in the form of a metalline or a contact portion, depending on the device requirements.Thereafter, a metal may be filled in the opening, wherein respectivetechniques may be used, as will be described with reference to themetallization layer 120 and subsequent embodiments described withreference to the further drawings. Thus, after completing themetallization layer 110, the dielectric material 121 may be deposited,for instance by using appropriate techniques for applying a low-kmaterial, followed by sophisticated patterning techniques for forming anopening for the via 122B and the trench 122A. It should be appreciatedthat, in the embodiment shown in FIG. 1 a, the openings for the via 122Band the trench 122A may have been formed so as to connect to each otherin order to enable a common filling in of the barrier material 123 andthe highly conductive metal, such as copper. In other cases, the via122B and the trench 122A may be formed in separate patterning sequences,which may also be encompassed by the principles disclosed herein.

In the following description, it may be referred to as a process forcommonly filling the via 122B and the trench 122A, which may also bereferred to as a dual damascene approach. Thus, the barrier layer 123may be deposited by using well-established techniques, such as sputterdeposition, chemical vapor deposition (CVD), atomic layer deposition(ALD), electrochemical deposition and the like. Thereafter, the highlyconductive metal may be deposited, wherein, frequently, a so-called seedlayer may be provided, which may also be deposited on the basis ofsputter deposition, ALD, CVD, electrochemical deposition and the like.Next, the volume material may be deposited, for instance, by electrolessplating, electroplating and the like. Typically, excess material may bedeposited so as to reliably fill the via 122B and the trench 122A,thereby requiring a subsequent removal of the excess material in orderto provide the metal region 122 as an isolated feature. A respectiveremoval of excess material may be accomplished by using removaltechniques such as chemical mechanical polishing (CMP), electro-CMP,etching, electro-etching and the like. Consequently, after the end ofthis process sequence, the surface 122S may be exposed. In someillustrative embodiments, the exposed surface 122S may be treated, whenhighly reactive metals, such as copper, are used for the metal region122. That is, during the removal of the excess material and in anysubsequent substrate handling processes, the exposed surface 122S maycome into contact with reactive components, such as fluorine, oxygen andthe like, which may result in the creation of a locally varying degreeof surface contamination. Hence, in some illustrative embodiments, apassivation layer 124, for instance in the form of copper oxide and thelike, may be provided to obtain enhanced uniformity during the furtherprocessing for selectively providing a metallic species in and at thesurface 122S. For example, after exposing the surface 122S, an oxidizingambient may be established in order to controllably create a thin copperoxide layer, which may continuously cover the surface 122S.

FIG. 1 b schematically illustrates the semiconductor device 100 in afurther advanced manufacturing stage. As shown, a mask 102, which may beprovided in the form of a resist mask, is formed above the metallizationlayer 120 and includes an opening 102A for exposing the surface 122S orthe corresponding passivation layer 124, if provided. The mask 102 maybe patterned on the basis of a lithography step using the same mask aspreviously used for patterning the trench 122A. During the applicationof the resist material and the subsequent patterning and post-exposuretreatment, the passivation layer 124 may suppress any interaction withthe material in the trench 122A. After patterning of the mask 102, asurface treatment process 103 may be performed to selectively introducea desired metallic species, such as nickel, tin, cobalt and the like. Insome illustrative embodiments, the atomic radius of the metal speciesmay be comparable and advantageously greater than the atomic radius ofcopper, thereby reducing inter-diffusion of the metallic species duringthe further processing and the operation of the device 100. In oneillustrative embodiment, the treatment 103 may comprise a plasmatreatment performed in plasma ambient containing the desired metallicspecies. For this purpose, any appropriate process tool for plasmaassisted deposition or etching may be used for establishing the plasmaambient, wherein appropriate process parameters, such as plasma power,bias power and the like, may be determined by experimentally determininga penetration depth and a concentration of the metallic species for aplurality of different process conditions. In some illustrativeembodiments, the treatment 103 may include a preceding cleaning process,for instance, for removing surface contamination or the passivationlayer 124, if deemed inappropriate for the incorporation of the desiredmetallic species.

In other illustrative embodiments, the surface treatment process 103 maycomprise an ion implantation process, which may be performed on thebasis of appropriately adjusted process parameters, such as implantationenergy, dose and the like. For example, moderately low implantationenergies of several keVs to several tens of keVs may be used incombination with implantation species, such as nickel, tin, cobalt andthe like. Respective parameter settings may be readily established bysimulation and/or experiment in order to obtain a desired penetrationdepth and concentration. For example, the metallic species may beincorporated into the surface 122S with a thickness of one to severalnanometers, thereby generating a surface layer 122L containing a desiredconcentration of the metallic species under consideration. For instance,a concentration of approximately 0.05 to several atomic percent may beincorporated during the process 103, thereby enhancing the overallsurface characteristics, as previously discussed. It should beappreciated that the passivation layer 124, if provided, may bemaintained in some cases, wherein the implantation energy may beappropriately adjusted to obtain the desired penetration depth andthickness of the layer 122L after removing the passivation layer 124 atany appropriate manufacturing stage.

FIG. 1 c schematically illustrates the semiconductor device 100 afterthe removal of the mask 102. Consequently, the metal region 122 maycomprise the layer 122L of enhanced electromigration behavior, possiblyin combination with the passivation layer 124. The further processingmay then be continued by depositing a dielectric cap layer, for instancein the form of silicon nitride, silicon carbide, nitrogen-containingsilicon carbide and the like, followed by the deposition of thedielectric material of a following metallization layer. It should beappreciated that, in some illustrative embodiments, a heat treatment maybe performed after the incorporation of the metallic species 122L topromote the formation of an alloy and thus stabilize the characteristicsof the layer 122L. For example, during this heat treatment, thecrystallographic configuration of the metal in the region 122 may alsobe adjusted, for instance, in view of grain size, grain orientation andthe like.

FIG. 1 d schematically illustrates the semiconductor device 100according to further illustrative embodiments. The device 100 is shownin a manufacturing stage in which a metal layer 122M may have beenformed, on the basis of deposition techniques, as previously described.Thus, the metal layer 122M may be formed above the dielectric material121 and within the opening defining the metal region 122.

FIG. 1 e schematically illustrates the device 100 during the treatment103, which now comprises an ion implantation process based on processparameters to introduce the metallic species down to a desired depth, asindicated by arrow 122D and the dashed line. As illustrated, theconductive barrier layer 123 may cover the dielectric material 121 andmay thus provide ion stopping capabilities, depending on the compositionof the barrier layer 123. In other cases, the surface topography of thelayer 123 may in itself provide increased penetration of the metalregion 122 due to a reduced height level with respect to the heightlevel defined by the dielectric material 121. Thus, the implantationenergy may be adjusted such that significant penetration into thedielectric material 121 may be prevented, while, nevertheless, obtaininga desired concentration of the metallic species at a height level withinthe region 122, which may correspond at least to the surface after theremoval of the excess material of the layer 122M. Moreover, during asubsequent removal process, which may comprise a CMP process, thebarrier layer 123 may have to be reliably removed from horizontalportions of the dielectric material 121, thereby typically requiring acertain degree of over-polishing, during which a certain amount of thedielectric material 121 may also be removed. Consequently, undesiredmetallic species contained therein may also be reliably removed, sincethe implantation energy may be selected such that the penetration depthis restricted to a portion of the dielectric material 121, which may bereliably removed during the subsequent CMP process.

FIG. 1 f schematically illustrates the device 100 after removal of theexcess material. As illustrated, the metallic species in the form of thelayer 122L may be provided on the metal region 122, while acontamination of the dielectric material 121 may be maintained at a lowlevel, as discussed above. Thereafter, the further processing may becontinued, for instance, by performing a heat treatment and the like,followed by the deposition of an appropriate dielectric cap material,possibly in combination with a further metallization level. Hence, theimplantation process 103 as shown in FIG. 1 e may be performed as a“self-masking” and self-adjusted process, since the metallic species maybe substantially positioned in and on the metal region 122, whileundesired amounts of the metallic species, if incorporated in thedielectric material 121, may be subsequently removed without requiringadditional process steps.

FIG. 1 g schematically illustrates the semiconductor device 100according to still further illustrative embodiments, in which, startingfrom the configuration as shown in FIG. 1 d, a first removal step 104may be performed to reduce an initial thickness of the layer 122M to asecond excess height 122H, thereby also providing a substantially planarsurface topography. In some illustrative embodiments, the excess height122H may be substantially zero, thereby exposing the barrier layer 123,which may provide enhanced controllability of the removal process 104.Thus, based on enhanced surface topography and the defined excess height122H, the process parameters of the subsequent implantation process 103may be adjusted with enhanced accuracy, thereby providing increasedprocess uniformity and thus uniformity of the layer 122L.

FIG. 1 h schematically illustrates the device 100 during the process103, thereby positioning the metallic species at a desired depth forforming the layer 122L, wherein significant penetration of thedielectric material 121 may be blocked by the barrier material 123and/or may occur with increased uniformity, thereby also enhancing theresult of the subsequent removal of the barrier layer 123 including themetallic species. In other illustrative embodiments, the excess height122H may be approximately zero, thereby exposing the surface 122, whilesubstantially maintaining the barrier layer 123. In this case,appropriate plasma treatments may be performed, thereby providing adesired penetration depth, which may result in enhanced cycle time anduniformity, substantially without contributing to a contamination of thedielectric material 121. Thereafter, the barrier material 123 and anyexcess material of the layer 122M may be removed and the furtherprocessing may be continued, as described above.

FIG. 1 i schematically illustrates the device 100 according to stillfurther illustrative embodiments, in which the mask 102 may be used as adeposition mask for selectively forming the layer 122L, which maycomprise the desired metallic species, while substantially avoiding thecontact of the layer 122L with the dielectric material 121. For example,electro-chemical deposition techniques may be used, for instance,preceded by the deposition of an appropriate catalyst material, if theexposed surface 122S (see FIG. 1 j) may be considered inappropriate fora desired electrochemical deposition. In other cases, theelectrochemical deposition process may be a self-catalyzing process,thereby substantially avoiding the deposition of the layer 122S onexposed portions of the mask 102. Thus, the mask 102 may reliablysuppress a contact of the material 121 with a corresponding electrolytesolution. The mask 102 may be efficiently removed on the basis ofwell-established techniques. In other illustrative embodiments, thelayer 122S may be deposited on the basis of a gaseous ambient, forinstance, by performing a physical vapor deposition process or achemical vapor deposition process, wherein a process temperature may bemaintained at approximately 200° C. and less to avoid significantchemical modifications in the structure of the mask 102, if provided asa resist mask.

After the deposition of the layer 122S including the metallic species,the mask 103 may be removed, for instance, by applying heat so as topeel off the mask 103 together with the layer 122S. It should beappreciated that, during the corresponding removal process,contamination of exposed portions of the dielectric material 121 mayremain at a low level since removed pieces of the layer 122S may notsubstantially come into contact with the dielectric material 121. Afterthe removal of the mask 103, a heat treatment may be performed, forinstance, for stabilizing the layer 122S and/or for generating a certaindegree of inter-diffusion or to promote the formation of an alloy toenhance the overall strength of the surface 122S comprising the layer122L.

FIG. 1 j schematically illustrates the device 100 with the layer 122Lselectively formed on the surface 122S. For example, the layer 122L mayrepresent the result of the process after removing the mask 102, while,in other illustrative embodiments, the layer 122L may be deposited abovethe metal region 122 and the dielectric material 121 if significantreaction of the metallic species in the layer 122L with the dielectricmaterial 121 may not substantially occur at temperatures used during thedeposition of the layer 122L and the subsequent patterning thereof. Forexample, a lithography mask may be formed after the deposition of thelayer 122L and exposed portions thereof, i.e., portions not formed onthe dielectric layer 121, may be removed on the basis of any appropriateetch techniques.

FIG. 1 k schematically illustrates the device 100 during a heattreatment 104 for initiating a diffusion of the metallic species withinthe layer 122L into the metal of the metal region 122. In someillustrative embodiments, the layer 122L may be removed after theprocess 104 if a direct contact with a further dielectric material maybe deemed inappropriate. Hence, the layer 122L may act as a donator forthe desired metallic species during a heat treatment 106, whilesubstantially not affecting the dielectric material 121.

As shown in FIG. 1 l, after the anisotropic etch process, a further etchprocess 105 may be performed that is designed to remove the remainingmaterial of the etch stop layer 114 within the via opening 121A. Forexample, the remaining etch stop material may be removed during theremoval of a corresponding resist mask using an oxygen-based plasmaambient, possibly in combination with a fluorine component. Hence, afterthe etch process 105, a portion of the surface of the metal region 112may be exposed, as indicated by 112S. That is, the portion 112S may havesubstantially the lateral dimension as the via 122B to be formed in thevia opening 121A.

FIG. 1 m schematically illustrates the device 100 during the ionimplantation process 103 for introducing the metallic species into theexposed surface portion 112S on the basis of appropriately selectedimplantation parameters. Thus, a respective layer 122L may be created ata portion at which the via 122B will connect to the metal region 112,thereby providing enhanced electromigration stability at this area. Itshould be appreciated that a metallic species may also be incorporatedinto the surface portion of the dielectric material 121, wherein,however, a penetration depth may be moderately low since lowimplantation energies may be used, as the layer 122L may be required atthe surface portion 112S only. Consequently, during the furtherprocessing, that is, during a patterning process for forming a trenchopening and a subsequent filling of the via opening 121A and theoverlying trench opening, the barrier material 123 and the metal layer122M (FIG. 1 d) may be deposited, as described above. In someillustrative embodiments, in this stage, the metallic species may beincorporated, for instance, by an ion implantation process, aspreviously described, while, in other cases, the metallic species may beapplied at a later manufacturing stage, as described with the precedingembodiments. In still other cases, the layer 122L in the exposed surfaceportion 112S may be considered sufficient for obtaining the desiredenhancement in electromigration resistance. In any case, the excessmaterial of the layer 122M may be removed by a process, including a CMPprocess, at least at a final phase, thereby also removing a certainamount of the dielectric layer 121, as previously explained. Hence,during this removal process, the metallic species formed in a surfaceportion of the dielectric layer 121 may be significantly reduced or maybe substantially completely removed, thereby reducing or suppressing anegative effect on the dielectric characteristics of the layer 121.

As a result, the principles disclosed herein provide techniques forenhancing the electromigration behavior of metallization systems ofadvanced semiconductor devices by “selectively” providing a metallicspecies at least on a portion of the surface of a metal region. For thispurpose, in illustrative aspects, an implantation process may beperformed on the basis of an implantation mask or on the basis ofself-masking mechanisms and/or a selective deposition and diffusionmechanism may be employed. By using an implantation process forselectively incorporating a metallic species, the implantationparameters may be appropriately tuned to obtain a desired resistivity ofthe implanted portion of the basis material. That is, since implantationparameters such as dose and energy may be finely tuned for any givenmetallic species, the overall concentration and the verticalconcentration profile may be appropriately adjusted so as to not undulyincrease the overall resistivity of the implanted portion and thus ofthe metal region under consideration but nevertheless provide anenhanced resistance against electromigration effects. Consequently, theoverall electrical resistivity of metal lines may not be undulyincreased while nevertheless significantly enhancing the interfacecharacteristic with an overlying dielectric cap layer. On the otherhand, unwanted interaction of the metallic species with the dielectricmaterial may be suppressed or substantially completely avoided, therebymaintaining additional leakage currents at a low level.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. For example, the process steps set forth above may beperformed in a different order. Furthermore, no limitations are intendedto the details of construction or design herein shown, other than asdescribed in the claims below. It is therefore evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention. Accordingly, the protection sought herein is as set forth inthe claims below.

1. A method, comprising: forming a mask above a metal region formed in adielectric material of a metallization layer of a semiconductor device,said mask exposing a surface of said metal region and covering saiddielectric material; applying a metallic species through said mask tosaid exposed surface of said metal region; removing said mask; andforming a dielectric cap material above said metallization layer, saiddielectric cap material covering said surface containing said metallicspecies.
 2. The method of claim 1, wherein applying said metallicspecies comprises performing an ion implantation process to introduceions of said metallic species into said surface.
 3. The method of claim1, wherein applying said metallic species comprises performing plasmatreatment in a plasma ambient containing ions of said metallic species.4. The method of claim 1, wherein applying said metallic speciescomprises forming a metal layer comprised of said metallic species onsaid exposed surface.
 5. The method of claim 4, wherein forming saidmetal layer comprises performing an electrochemical deposition process.6. The method of claim 4, wherein forming said metal layer comprisesdepositing said metallic species by at least one of a chemical vapordeposition process and a physical vapor deposition process.
 7. Themethod of claim 1, wherein said metallic species has an atomic radiusthat is greater than an atomic radius of copper.
 8. The method of claim1, further comprising forming a lower metallization layer prior toforming said metallization layer, wherein said lower metallization layercomprises a metal line, wherein said method further comprises formingsaid dielectric material above said lower metallization layer, forming avia opening in said dielectric material to expose a portion of saidmetal line and introducing said metallic species into a surface of saidexposed portion.
 9. The method of claim 8, wherein said metallic speciesis introduced by implanting said metallic species through said viaopening.
 10. A method, comprising: forming a metal layer above adielectric layer of a metallization layer of a semiconductor device soas to fill an opening in said dielectric layer; performing animplantation process to introduce a metallic species through an exposedsurface of said metal layer; and removing excess material of said metallayer from said dielectric layer to form a metal region in saiddielectric layer, said metal region having a surface comprising saidmetallic species.
 11. The method of claim 10, further comprising forminga conductive barrier material on said dielectric layer and an innersurface of said opening prior to forming said metal layer.
 12. Themethod of claim 11, wherein forming said metal layer comprisesdepositing said metal layer by performing an electrochemical depositionprocess.
 13. The method of claim 10, wherein said metal layer comprisescopper and said metallic species is a non-copper containing species. 14.The method of claim 13, wherein said metallic species has an atomicradius that is greater than an atomic radius of copper.
 15. The methodof claim 10, wherein forming said metal layer comprises depositing ametal material with a first excess height and removing a portion of saidmetal material to obtain a second reduced excess height.
 16. The methodof claim 10, further comprising forming a lower metallization layerprior to forming said metallization layer, wherein said lowermetallization layer comprises a metal line and wherein said methodfurther comprises forming said dielectric layer above said lowermetallization layer, forming a via opening in said dielectric layer toexpose a portion of said metal line and introducing said metallicspecies into a surface of said exposed portion.
 17. The method of claim16, wherein said metallic species is introduced by implanting saidmetallic species through said via opening.
 18. A method, comprising:forming a via opening in a dielectric layer, said via opening extendingto and exposing a portion of a metal region formed in a firstmetallization layer of a semiconductor device; performing an ionimplantation process to introduce a metallic species into said exposedportion of said metal region; and filling said via opening with a metal.19. The method of claim 18, further comprising forming a trench in saiddielectric layer, filling said trench with said metal to form a metalline and providing said metallic species at a surface of said metalline.
 20. The method of claim 19, wherein providing said metallicspecies at the surface of said metal line comprises forming a mask abovesaid dielectric layer to expose said surface and applying said metallicspecies on the basis of said mask.
 21. The method of claim 19, whereinproviding said metallic species at the surface of said metal linecomprises forming a metal layer when filling said trench, introducingsaid metal species into said metal layer and removing excess material ofsaid metal layer to expose said surface containing said metallicspecies.